1. Field of the Invention
The present invention generally relates to an interconnection substrate and a manufacturing method thereof and, more particularly, to an interconnection substrate and a manufacturing method thereof which are useful in reducing stress that occurs between the interconnection substrate and a semiconductor element mounted thereon.
2. Description of the Related Art
Recently, as electronic machines have shrunk in size, semiconductor devices mounted thereon have also been miniaturized. One of these miniaturized semiconductor devices is a CSP (Chip-Size Package). The CSP (hereinafter referred to as semiconductor package) is a multilayer interconnection substrate on which semiconductor elements such as an LSI chip are directly mounted by solder bumps or pins.
FIG. 1A is a cross-sectional view of the conventional semiconductor package. FIG. 1A shows a multilayer interconnection substrate 101 and a semiconductor element 105 to be mounted thereon. As shown in the figure, the semiconductor element 105 has electrodes 107. Each of the electrodes 107 has a column 106 composed of conductive metals. The column 106 has a solder bump 104 on its end. A resin layer 103 protects water penetrating to the semiconductor element 105.
The multilayer interconnection substrate 101 has terminal pads 102 in its uppermost layer. The above-mentioned semiconductor element 105 is then mounted on the multilayer interconnection substrate 101 so that the solder bump 104 is welded to each of the terminal pads 102 with pressure. Thereafter, by reflowing the solder bump 104, the semiconductor element 105 is electrically and mechanically connected to the multilayer interconnection substrate 101. FIG. 1B is a cross-sectional view of the multilayer interconnection substrate 101 and the semiconductor element 105 mounted thereon in the above-mentioned manner.
Generally, the multilayer interconnection substrate 101 and the semiconductor element 105 have different coefficients of thermal expansion. Thus, the multilayer interconnection substrate 101 and the semiconductor element 105 undergo different amounts of thermal contraction during cooling down after the reflowing of the solder bump 104. Two arrows in FIG. 1B indicate the amounts and directions of the thermal contraction which the multilayer interconnection substrate 101 and the semiconductor element 105 undergo.
The above-mentioned column 106 relaxes stress which is caused by the different amounts of thermal contraction of the multilayer interconnection substrate 101 and the semiconductor element 105 and acts therebetween. A description will be given, with reference to FIG. 2, of this point.
FIG. 2A is a cross-sectional view of the column 106 immediately after mounting the semiconductor element 105 and reflowing the solder bump 104. At this point, the whole body is still at a high temperature, and the multilayer interconnection substrate 101 and the semiconductor element 105 have not started thermal contraction yet.
FIG. 2B is a cross-sectional view of the column 106 quite a long time after mounting the semiconductor element 105 and reflowing the solder bump 104. In this figure, the multilayer interconnection substrate 101 and the semiconductor element 105 have undergone thermal contraction. The different amounts of thermal contraction of the multilayer interconnection substrate 101 and the semiconductor element 105 have resulted in stress, which has made the column 106 inclined, as shown in FIG. 2B.
The inclining metal column 106 relaxes the stress which acts on the solder bump 104. Therefore, this prevents the stress from separating the solder bump 104 from the terminal pad 102 provided on the multilayer interconnection substrate 101. This also prevents the stress from acting on and cracking the semiconductor element 105.
The above-mentioned column 106 is formed on the semiconductor element 105 in a post-process thereof, that is, after a pre-process of manufacturing the semiconductor element 105.
However, forming the column 106 in the post-process prolongs the duration of the post-process to that extent. This increases the possibility of the semiconductor element 105, which is completed in itself in the pre-process, falling inferior in the prolonged post-process and, thus, decreases the yield rate of the costly semiconductor elements.
It is a general object of the present invention to provide an improved and useful interconnection substrate and a manufacturing method thereof in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide an interconnection substrate having metal columns covered by a resin film and a manufacturing method thereof which can relax stress, caused originally by different coefficients of thermal expansion between a multilayer interconnection substrate or the interconnection substrate and the semiconductor element mounted thereon, not on the side of the semiconductor element, but on the side of the substrate.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a multilayer interconnection substrate comprising:
an uppermost interconnection layer having a plurality of terminal pads formed at positions corresponding to a plurality of external connection terminals provided on a semiconductor element which is to be mounted on the multilayer interconnection substrate;
a metal column formed on each of the terminal pads;
a resin film covering a side surface of the metal column; and
an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
Additionally, in the present invention, a height of the metal column may be smaller than a thickness of the insulating layer.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a multilayer interconnection substrate manufacturing method comprising the steps of:
forming a plurality of terminal pads in an uppermost interconnection layer;
forming an insulating layer on the uppermost interconnection layer;
forming openings in the insulating layer, the openings located at positions corresponding to the terminal pads;
filling each of the openings with metal particles;
forming a metal column in each of the openings by heating the metal particles at a temperature which melts the metal particles; and
removing a part of the insulating layer near but not adjacent to a peripheral side of the metal column, while leaving a part of the insulating layer adjacent to the peripheral side of the metal column, so that a gap is formed around but not adjacent to the peripheral side of the metal column.
Additionally, in the present invention, the step of filling may include a step of filling each of the openings with the metal particles up to a predetermined level in the middle of each of the openings.
In order to achieve the above-mentioned objects, there is also provided according to still another aspect of the present invention a multilayer interconnection substrate manufacturing method comprising the steps of:
forming a plurality of terminal pads in an uppermost interconnection layer;
forming an insulating layer on the uppermost interconnection layer;
forming openings in the insulating layer, the openings located at positions corresponding to the terminal pads;
forming a conductive layer on surfaces of the insulating layer and inner surfaces of the openings;
forming a plating metal on the conductive layer by electrolytic plating by using the conductive layer as an electric supply layer so that the plating metal fills the openings;
forming a metal column in each of the openings by removing other parts of the conductive layer and the plating metal than a part formed in each of the openings by one of etching and polishing so that the conductive layer and the plating metal together form the metal column; and
removing a part of the insulating layer near but not adjacent to a peripheral side of the metal column, while leaving a part of the insulating layer adjacent to the peripheral side of the metal column, so that a gap is formed around but not adjacent to the peripheral side of the metal column.
In order to achieve the above-mentioned objects, there is further provided according to still another aspect of the present invention a multilayer interconnection substrate manufacturing method comprising the steps of:
forming a plurality of terminal pads in an uppermost interconnection layer;
forming a conductive layer on the terminal pads;
forming a plating resist on the conductive layer;
forming openings in the plating resist, the openings located at positions corresponding to the terminal pads, so as to expose a part of the conductive layer formed on each of the terminal pads at the bottom of each of the openings;
forming plating metals on the part of the conductive layer exposed at the bottom of each of the openings by electrolytic plating by using the conductive layer as an electric supply layer so that the plating metals form a metal column in each of the openings;
removing the plating resist so as to expose parts of the conductive layer other than a part where the metal column is formed;
removing the exposed parts of the conductive layer other than the part where the metal column is formed by etching;
forming an insulating layer all over the uppermost interconnection layer, leaving an upper surface of the metal column uncovered; and
removing a part of the insulating layer near but not adjacent to a peripheral side of the metal column, while leaving a part of the insulating layer adjacent to the peripheral side of the metal column, so that a gap is formed around but not adjacent to the peripheral side of the metal column.
Additionally, in the present invention, the conductive layer may be composed of a metal containing copper, the metal column may be composed of solder, and the step of removing the exposed parts of the conductive layer may be performed using an etching solution, an etching rate of the etching solution with respect to copper being higher than an etching rate of the etching solution with respect to solder.
The multilayer interconnection substrate according to the present invention has the uppermost interconnection layer having a plurality of the terminal pads and the metal column formed on each of the terminal pads. The resin film covers the side surface of the metal column. The insulating layer is formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and the outer peripheral surface of the resin film.
The above-mentioned metal column is formed so as to correspond to each of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the multilayer interconnection substrate. The metal column is to be electrically connected to each of the solder bumps.
According to the multilayer interconnection substrate having this structure, the metal column relaxes stress caused between the multilayer interconnection substrate and the semiconductor element mounted thereon. That is, the metal column can be inclined to relax the stress caused originally by different coefficients of thermal expansion between the multilayer interconnection substrate and the semiconductor element mounted thereon.
Additionally, in reflowing the solder bumps, covering the side of the metal column with the resin film prevents the melted solder from flowing down the outer peripheral surface of the resin film. That is, the upper surfaces of the resin film and the metal column have different affinities to the melted solder, and thus the melted solder does not spread over the upper surface of the resin film, let alone flow down the outer peripheral surface of the resin film.
It should be noted that the height of the metal column may be smaller than the thickness of the insulating layer. Forming the metal column in this manner eases registration of the semiconductor element and the multilayer interconnection substrate when mounting the semiconductor element onto the multilayer interconnection substrate, compared with a case where the height of the metal column is not smaller than the thickness of the insulating layer.
That is, if the center of each of the solder bumps formed on the semiconductor element and the center of the corresponding metal column are not accurately aligned, in the course of bringing the semiconductor element nearer to the multilayer interconnection substrate, the solder bump contacts a periphery of the insulating layer around the metal column. Then, the whole semiconductor element is automatically guided so that each of the solder bumps is also guided toward the upper surface of the corresponding metal column, and eventually, each of the solder bumps adjoins the upper surface of the metal column.
Therefore, there is no need to accurately align the center of each of the solder bumps and the center of the corresponding metal column when mounting the semiconductor element onto the multilayer interconnection substrate.
Further, the metal column is formed not on the semiconductor element, as a conventional column, but on the multilayer interconnection substrate. Therefore, a post-process of manufacturing the semiconductor element does not need to be prolonged to form the metal column. This shortens the duration of the post-process of manufacturing the semiconductor element and thus reduces the possibility of the semiconductor element falling inferior in the post-process, compared with a case of the conventional column formed on a semiconductor element.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention an interconnection substrate comprising:
an insulating base having a plurality of penetration holes;
a plating metal filling each of the penetration holes;
a terminal pad formed on an end of each of the penetration holes so that the terminal pad is connected to the plating metal, the terminal pad located at a position corresponding to a respective one of a plurality of external connection terminals provided on a semiconductor element which is to be mounted on the interconnection substrate;
a metal column formed on the terminal pad;
a resin film covering a side surface of the metal column; and
an insulating layer formed on a surface of the insulating base on the same side as the above-mentioned end of each of the penetration holes so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
In order to achieve the above-mentioned objects, there is also provided according to still another aspect of the present invention an interconnection substrate manufacturing method comprising the steps of:
forming an insulating base having a plurality of penetration holes therein and a conductive layer for terminal pads formed on one surface thereof;
forming a plating resist on the conductive layer for terminal pads;
forming openings in the plating resist, the openings located at positions corresponding to each of the penetration holes, so as to expose a part of the conductive layer for terminal pads at the bottom of each of the openings;
filling the penetration holes and the openings respectively with plating metals by electrolytic plating by using the conductive layer for terminal pads as an electric supply layer so that the plating metals form a metal column in each of the openings;
removing the plating resist so as to expose parts of the conductive layer for terminal pads other than a part where the metal column is formed;
removing the exposed parts of the conductive layer for terminal pads other than the part where the metal column is formed by etching so as to expose a surface of the insulating base, leaving the part where the metal column is formed as a terminal pad;
forming an insulating layer on the exposed surface of the insulating base, leaving an upper surface of the metal column uncovered; and
removing a part of the insulating layer near but not adjacent to a peripheral side of the metal column, while leaving a part of the insulating layer adjacent to the peripheral side of the metal column, so that a gap is formed around but not adjacent to the peripheral side of the metal column.
Additionally, in the present invention, the conductive layer for terminal pads may be composed of a metal containing copper, the metal column may be composed of solder, and the step of removing the exposed parts of the conductive layer for terminal pads may be performed using an etching solution, an etching rate of the etching solution with respect to copper being higher than an etching rate of the etching solution with respect to solder.
The interconnection substrate according to the present invention provides the same functions as the above-mentioned multilayer interconnection substrate according to the present invention.
The interconnection substrate has a plurality of the penetration holes (via holes) and the plating metals filling the penetration holes. On the one end of each of the penetration holes is formed the terminal pad so as to be connected to each of the plating metals. On the terminal pad is formed the metal column. The resin film covers the side surface of the metal column. The insulating layer is formed on the surface of the insulating base, on the same side as the one end of each of the penetration holes.
There is the gap between the outer peripheral surface of the resin film and the insulating layer. The metal column is formed so as to be located at a position corresponding to a respective one of a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The metal column is to be electrically connected to each of the solder bumps.
The metal column, the resin film and the insulating layer provided for the interconnection substrate according to the present invention have the same functions as the metal column, the resin film and the insulating layer provided for the above-mentioned multilayer interconnection substrate according to the present invention, respectively. Thus, the metal column, the resin film and the insulating layer provided for the interconnection substrate according to the present invention give the same effects as the metal column, the resin film and the insulating layer provided for the above-mentioned multilayer interconnection substrate according to the present invention, respectively.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.